Design Verification (DV) Engineer, VHDL / UVM Simulations (96)
Job Title Design Verification (DV) Engineer, VHDL / UVM Simulations
Location Locate at one of several sites closest to candidate home, see below
Job # 96/5177
Residency US Citizens Only
Clearance Active Secret
Duration 9-12 months
Pay Rate $95/hr
Per diem Yes split available that can net about 1000 extra per month to cover lodging
Overtime Unknown details at interview
Shifts Every other Fri is off (9x80)
Notes Position can be based in Austin, North NJ, NH, MA, Manassas VA or San Diego
We seek a hands-on design verification engineer to conduct DV planning, develop test bench infrastructure (environment, stimulus generators, monitors, predictors, checkers), develop testcases. run simulations, and assist with the diagnosis of functional issues found during simulations.
Applicant regularly works with design requirements to understand design intent and implementation, and to assist in the debug of issues found during simulations.
*7 years’ experience in developing VHDL or SystemVerilog and use of UVM code for verification.
*Active Secret Clearance, US Citizens only can apply.
*Experience using Git source code management or Siemens/Mentor QuestaSim tools. *Experience with Atlassian tools (like Jira, Bitbucket)
*Familiar with Makefiles and scripting with TCL, Python, Perl, etc.
*Can read RTL code implemented in VHDL